The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for generating code adapted for interlinking legacy scalar code and extended vector code.
Single Instruction Multiple Data (SIMD) is a technique utilized in processor architectures to achieve data level parallelism. The SIMD technique essentially means that the processor operates the same instruction on multiple data, thereby achieving parallel operation. SIMD is used in most vector units of vector computing devices. Scalar processors operate using a Single Instruction Single Data (SISD) technique in which the processor operates a single instruction on a single piece of data.
As an example, SIMD techniques may be used as a way of packing N (usually a power of 2) like operations, e.g., 8 add operations, into a single instruction. The data for the instruction operands is packed into registers capable of holding the extra data. The 8 add operations are then performed on the data as part of executing the single instruction. Thus, for the cost of doing a single instruction, N instructions worth of work are actually performed. This can result in increased processing speeds for parallelizable code.
Both the PowerPC™ architecture, available from International Business Machines Corporation of Armonk, N.Y., and the IA-32 architecture, available from Intel Corporation, have SIMD extensions to their vector architectures. On PowerPC, the extension is called AltiVec™. On the IA-32 architecture, the vector architecture extensions have been gradually introduced, at first as the Intel MultiMedia eXtensions (MMX) and then later as the Intel Streaming SIMD Extensions (SSE, SSE2, SSE3). Examples of common areas where SIMD can result in very large improvements in speed are 3-D graphics, image processing, video processing, theater-quality audio, high performance scientific calculations, and the like. SIMD units are present on all G4, G5 or Intel Pentium 3/4/M class processors.
While SIMD provides great performance improvements over traditional scalar approaches to executing code, not all code supports parallelization in SIMD and some legacy code is only available for scalar execution. That is, since the prior architectures focused on scalar execution, i.e. SISD, many legacy applications are not able to be executed using SIMD parallelization and are not compatible with newer SIMD code or are only currently offered as scalar code and it is too costly to recode the scalar code for use in a SIMD or vectorized environment. However, users may wish to take advantage of legacy applications without having to recode these applications for the new SIMD architecture. Furthermore, users may wish to use such legacy applications in connection with newer SIMD code. Currently, there are no mechanisms for allowing such interlinking of scalar and vector code, i.e. SIMD code.